The present invention relates generally to designing electronic circuits such as integrated circuits, and more particularly to synthesizing electronic circuits.
Modern integrated circuits often have millions of circuit elements such as gates, latches, and drivers in addition to scores of I/O pins. Rather than design such circuits on the gate level, designers often use a hardware description language (HDL) to describe the desired functionality of the circuit including timing constraints. The resulting description (e.g., in the form of HDL statements) is typically highly hierarchical in nature similar to software programs. The hierarchical HDL statements are then parsed and expanded by a synthesis program which converts the statements to circuit/logic elements such as gates and registers. The process of parsing, expanding, and conversion is known as logic synthesis.
Each of these circuit elements must then be sized, placed (e.g., in a design space corresponding to a chip), and electrically connected (routed) to other circuit elements, or to I/O pins, via wires (a.k.a. traces) to realize the desired functionality. The process of sizing, placing, and routing is known as physical synthesis.
One of the primary drivers behind conventional logical and physical synthesis is “circuit slack”. Circuit slack is a time measurement that indicates how much timing delay (budget) is available before the timing constraints are exceeded for a particular portion of the circuit. A negative circuit slack indicates that the circuit delay must be reduced to meet the timing constraints. The objective with conventional automated synthesis, placement and routing is to eliminate all negative slack values.
Conventionally, eliminating negative slack values requires an iterative approach that often requires manual intervention. Furthermore, the described processes have a high number of interdependencies which make automated optimization difficult. For example, the speed of circuit elements is typically dependent on the size of the transistors. In turn, the size of the circuit elements affects how far apart they must be spaced and the signal delay.